This invention relates generally to a semiconductor device. In particular, it relates to a master slice type gate array that uses a plurality of insulated gate field effect transistors (MIS transistors) as the basic cells.
The internal chip structure in the channel-less gate array of the prior art is composed of columns of cells in which a plurality of basic cells in the center of the silicon chip are arranged in regular horizontal and vertical rows. A plurality of input and output buffers surround the periphery of the silicon chip. In a gate array, the structure of the basic cells is important in terms of configuring the desired logic gates and logic blocks through wiring connections. One known example of a basic cell structure is disclosed in Japanese Patent No. 16174/91, as shown in FIG. 14.
As shown, basic cell 1 runs along well 2, which has a symmetrical shape from top to bottom and left to right, and along radial lines 1.sub.1 to 1.sub.4, which are centered on center point Q of well 2 gate surface. In addition, except for the area around center point Q, the basic cell has gate electrodes 3 formed on top of well 2. Each section of well 2 that is partitioned by gate electrode 3 is alternately in source region S and drain region D.
In basic cell 1, gate electrodes are oriented in a radial direction. Since the shape of the cell is symmetrical relative to top and bottom centerline 1.sub.2 and right and left center line 1.sub.1, it is possible to use the basic cell in the right and left symmetry and the top and bottom symmetry. This increases the degree of circuit design freedom and reduces unused region of the gates.
However, the basic cell described above has the following problems:
(1) A plurality of gate electrodes 3 are oriented in the radial direction relative to center point Q. Source regions S and drain regions D, which are partitioned by gate electrodes 3, are also individually oriented in the radial direction relative to center point Q. Therefore, in this basic cell, the tendency is to wire each electrode in the radial direction. As a result, although there is a high-level of freedom for external wiring for basic cell 1, there is a low-level of freedom for internal wiring of the transistors within basic cell 1. PA1 (2) In general, in the technology of the prior art, each gate electrode of the basic cell has wiring connection areas on both ends in the non-active regions, which facilitates wiring of the gate electrodes. However, as stated earlier, in basic cell 1 described above, because a plurality of gate electrodes 3 converge on the center of well 2, an inadequate amount of wiring connection area is available at the center. Thus, it is difficult to place wiring connections on the inner ends of gate electrodes 3. As a result, there is a low degree of freedom for wiring of the special gate electrodes.
Basic cell 1 has a basic cell structure that includes centrifugal characteristics. As shown in FIG. 14, as to wire connection areas 3a of gate electrodes 3, because a plurality of gate electrodes 3 converge on the center of well 2, it is difficult to put connections on the inner ends of gate electrodes 3. Therefore, they are placed only on the outer ends. As a result, in the case of internal cell wiring, detour wiring and long distance wiring between wiring connection areas 3a of the outer ends are unavoidable. Moreover, the mutual wiring between source region S and drain region D is difficult and the wiring within the cell is poor.
For these reasons, a purpose of this invention is to resolve the problems stated above. The invention provides for a basic cell that has top and bottom symmetry and left and right symmetry. The basic cell structure is configured to allow a high-level of freedom for the internal wiring within the basic cell. The basic cell structure allows the gate electrodes to have a wiring connection area on both ends.